“Semiconductor packaging has never been more critical”
(Majeed Ahmad, EE Times, 2021).
Advanced Semiconductor Packaging
Transistor- and chip-scaling is gradually reaching its (economical) limit. The next phase of semiconductor innovation to increase device performance and energy efficiency will strongly rely on novel IC packaging techniques, a trend which has become known as “More than Moore”. The opportunities of additive electrostatic printing in this field are very wide, ranging from wafer/chip marking, bumping, via filling or direct patterning of redistribution layers. For latter, Scrona’s printing engine with sub-micrometer resolution and line aspect ratios larger than 10:1 is an ideal match with the potential to reduce the cost 10x compared to conventional photolithographic fabrication.